Physical System Architect

Job Description

As a Physical System Architect you would be shaping Arms latest platform architectures for implementation with the latest chip process and packaging technologies, impacting projects both within Arm and across the wider semiconductor industry.In the Central Technology - Systems team, we have a diverse set of motivated engineers covering all aspects of system architecture. We work in partnership with the engineering teams to define Arms Client, Infrastructure, Automotive and IoT systems.Do you have experience in top-level System-on-Chip definition and follow-through to bring-up of new hardware This is your opportunity to join a small team where we share a passion for extracting the maximum performance and power efficiency from the verylatest process technologies!Possible candidates may have a range of job experience from ambitious engineers early in their career to Senior Principal professionals, with corresponding flexibility in the job grade.Responsibilities:

• Develop hardware schemas and high level software flows for system partitioning into chiplets using 2.5D and 3D packaging considering signal interfaces, power delivery, system control and thermal constraints.
• Create architecture specifications for internal engineering teams and external documentation.
• Specify validation strategies for system-wide clock and power control schemes, including DI/dt droop mitigation and ensure efficient feedback of learning to future system generations.
• Develop and agree specifications with third party IP suppliers. E.g. Die-to-die phys, PLLs, process monitors, timing paths sensors.

Required Skills and Experience :

• B.Sc. in Electronic, Electrical or Computer Engineering. Other degrees will also be considered with relevant experience.
• Experience in SoC definition and New Product Introduction or product engineering, preferably involving CPUs and/or GPUs.
• Experience of working in cross-disciplinary engineering teams.
• Good understanding of the latest Silicon process roadmaps and consequences for SoC architecture.
• Experience with ASIC power state management such as power gating, clock gating, Adaptive Voltage Scaling (AVS) as well as Dynamic Voltage and Frequency Scaling (DVFS).

Nice To Have:

• Experience with top-level SoC power analysis and design verification
• Experience in silicon bring-up, validation, test, production or yield engineering
• Knowledge of on-chip and in-package Switch Mode Power Supply and LDO design

Personal Attributes:

• Creative personality, with strong problem-solving skills
• Ability to adapt approach between project definition to execution phase
• Ability to work in a collaborative, diverse and inclusive environment across time zones
• Excellent verbal, written and interpersonal communication skills

In Return:We offer a competitive reward package including annual bonus, RSUs, healthcare and wellness support. As well as other benefits such as a supplementary pension, and 25 days annual leave (with option to buy an additional 5 days per year). Theres even an on-sitegym and social events organised within the company!We are offering a hybrid approach to home and office working to provide an adaptable experience for all employees. We expect some working time to be spent in office, to promote a strong collaborative environment with good team integration but are accommodatingto different home working requirements.#LI-SM1