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| Job Location | Rickmansworth |
| Education | Not Mentioned |
| Salary | 90,000 - 110,000 per annum |
| Industry | Not Mentioned |
| Functional Area | Not Mentioned |
| Job Type | Permanent , full-time |
A Principal Digital IF Engineer with expertise in FPGA code design, synthesis, implementation and test is wanted by an award winning satellite communications engineering company. This is a permanent role with a salary on offer in the range of £90,000 -£110,000. Due to the nature of the role requiring lab time, this role is Hybrid with 3 days per week in the office which is located in Rickmansworth, Hertfordshire.Role summary:You will be working as a part of a small team and reporting to Digital RF Team Lead. The role will suit someone with a strong background in network protocols, and a working knowledge of communications systems engineering and digital signal processing. You willprobably have worked in software radio, or related discipline. A pragmatic approach to the implementation of FPGA based network equipment is essential. Ideally, you will have worked with SoC FPGAs such as Zynq or Cyclone device families. You will be responsiblefor implementing VITA-49 based network SDR transport protocols. You will have excellent FPGA skills, including working on mid-sized to large designs where there are multiple code authors operating in a cloud CI environment. You will take sampled signals, processthem, efficiently packetize and add context for data transmission over high speed ethernet. You will be able to size FPGA processing requirements, and have a working knowledge of the benefits of leading FPGA devices. You will be working on cutting-edge technologyas part of a multidisciplinary team in a fast-paced environment. You will rapidly gain skills in all technologies present in a complex digitization product line, working on some of the most complex and powerful FPGAs on the market today.Responsibilities will include:* Design and develop a range of modules and equipment for digital IF* Integration and test of digital IF equipment* Produce HDL code for VITA-49 or similar network SDR transport protocols* Ability to write & debug Linux drivers* Scripting in TCL designs utilizing IP Cores for rapid development* Build scripting to support continuous integration* Design and development of test benches to prove VHDL code* Conduct floor-planning and timing analysis of designs, achieving timing closure* Test of HDL code on target platform* Integration of firmware into application designThe person:* Experience of SDR protocols, such as VITA-49* Experience of FPGA implementations of communication stacks, including TCP/IP* Strong background with FPGA synthesis tools, ideally Synplify, Vivado, Quartus or* Mentor* Confident writing FPGA test benches* Able to efficiently implement DSP algorithms in VHDL and ideally experience of DSP algorithm simulator in MATLAB/PythonBenefits:* 25 days annual leave* Health benefits, such as enhanced sick pay, life assurance and free annual eye tests* Flexible working hours* Excellent internal support programme to allow for continued development* Visa sponsorship is available for this position