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| Job Location | Edinburgh |
| Education | Not Mentioned |
| Salary | 60,000 - 70,000 per annum |
| Industry | Not Mentioned |
| Functional Area | Not Mentioned |
| Job Type | Permanent,full-timeB |
JOB AD:Job DescriptionROLE OVERVIEWThis Senior role is part of a team that develops digital solutions for a new generation of mixed-signal motor control ASICs. In this position you will be responsible for the physical implementation of the main digital block of a mixed signal IC.RESPONSIBILITIES- Define the physical and timing constraints.- Define test requirements and insert scan logic.- Perform synthesis and place and route.- Construct the block floorplan, insert clock trees, timing optimization and static timing analysis.- Verify the integrity of the block power grid, estimate the power consumption and IR drop.- Ensure that the final database is logically correct using formal verification.- Confirm that the database is manufacturable by performing physical verification.- Automatic test pattern generation and vector verification.- Implement engineering change orders.KEY RELATIONSHIPSInternal- Provide feedback to the RTL designers and device team leader regarding RTL and timing constraint updates.- Coordinate with the top level layout engineers to ensure that the block footprint is correct.- Liaise with other physical design team members.External- Liaise with off-site design teams as required.- Communicate with other design teams, EDA and tool vendors to improve scripts and tool flowPERSON SPECIFICATIONQualificationsEssential:- The successful candidate will possess at least a degree in Electronics or related fields.- The prospective candidates should also have extensive relevant experienceDesirable:- Familiarity with Cadence Design Environment and Digital Tools- Experience of RTL synthesis including Scan Chain insertion and Synopsys Design Constraints (SDC) generation, TCL and/or Perl scripting Skills, Knowledge and Aptitudes- Knowledge of Synthesis, Floor -planning, Place and Route (P&R), Clock Tree Synthesis (CTS), Parasitic Extraction, Static Timing Analysis (STA), Timing Closure, Physical Verification and Formal Verification and ATPG.- Excellent communication, problem-solving and analytical skills.- Ability to work both within a team or standalone.TRAVEL REQUIREMENTSDomestic and international travel may be required in the role. The below provides an indication only of the amount, type and locations of travel. This is subject to change depending on business requirements.- National Travel: 5 - 10 %- International Travel: 5 - 10 %Travel Locations- Dependent on work that may arise, most likely Europe, the Americas or Asia