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| Job Location | Edinburgh |
| Education | Not Mentioned |
| Salary | 65,000 - 70,000 per annum |
| Industry | Not Mentioned |
| Functional Area | Not Mentioned |
| Job Type | Permanent , full-time |
JOB AD:In this position, you will be part of a growing and dynamic team that primarily focuses on developing mixed-signal motor drive ICs for industry leading customers. You will be responsible for architecting, implementing and verifying microcontroller-basedsystems and you will gain exposure to the latest trends in automotive motors control performance requirements, architectures and implementations.RESPONSIBILITIES- Analysis of design requirements, contribution to architectural decisions and writing of design specifications.- Verilog RTL design at both IP and SoC level, incorporating design-for-test.- Support verification via implementation of test-benches and RTL/gate-level simulation and debug.- Interface with physical implementation team for the definition of physical and timing constraints.- Contribute to the continuing evolution of the design flow and product quality by seeking out new methodologies and best practices.KEY RELATIONSHIPSInternal- Collaborate with digital design and verification engineers.- Interact with physical implementation design team.- Review of requirements with system engineers.- Interact with test engineers for ATPG programs.External- Liaise with off-site design teams as required.- Communicate with EDA and tool vendors.PERSON SPECIFICATIONQualificationsEssential:- Prospective candidates should have a PhD or Master degree (or equivalent) in Electronics or a related field and a solid experience with design in an embedded system.Desirable:- Strong knowledge of protocols for connecting CPUs, interconnect fabrics and peripherals together as well as knowledge of the various high level functions such as boot protocols, clocking, power, etc. required for large SOCs.- Experience in design and verification of the integration of peripheral IPs with the focus being on correctness of the interfaces and operation of the various full-chip SOC protocols.- Familiarity with Cadence toolsets.- Familiarity with DFT implementations such as scan, boundary scan and BIST techniques.- Familiarity with FPGA prototyping.Skills, Knowledge and Aptitudes- Competent in digital design techniques.- Strong skills in front-end RTL design using Verilog or VHDL.- Good knowledge of the overall front-to-back digital design flow.- Good verbal and written communication skills- Ability to work in a multi-cultural team environmentCandidates should also be able to demonstrate:- Good presentation skills in English and the ability to present information in a clear and concise manner- A high level of commitment and self-motivation- The ability to work as part of a world-wide development team with diverse engineering disciplines