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| Job Location | Manchester |
| Education | Not Mentioned |
| Salary | Salary negotiable |
| Industry | Not Mentioned |
| Functional Area | Not Mentioned |
| Job Type | Permanent , full-time |
Senior / Staff Verification Engineer - Permanent Position Based In Manchester or RemotelyBase Salary Is Negotiable Based On Skills/Experience PLUS Excellent Bonus & Benefits PackageThis Senior / Staff Verification Engineer will be joining a fast-paced technical environment, employing the latest hardware design and verification methodologies to develop complex and highly configurable System IP. Whether your verification expertise is with Interconnects, NoCs, SoCs or similar, the Senior / Staff Verification Engineer will work on highly scalable HW IP which is optimised for AMBA-compliant SoC connectivity and can be customised for multiple performancepoints.The Role:Specifying and developing new hardware verification testbenches for future generation hardware IP. You will improve existing testbenches to increase performance, quality and efficiency. You will also identify areas for improvement in processes andmethodologies, then implement those changes to advance best-practises and state of the art for hardware verification.Other responsibilities include reviewing and assessing proposed design changes from a verification complexity point of view.Taking ownership of verification environments from investigation all the way through to verification closure.Investigating and scripting new verification flows and optimising existing ones.Undertaking analysis of data from simulation runs using machine learning and data science techniques to drive efficient bug discovery and debugging.Where required, improving the verification methodology and mentoring other members of the teamWorking in close collaboration with other engineering teams to ensure high quality IP that works well in a complete system.Skills and Experience:Good experience working with constrained-random verification including ownership of a suitably complex verification environment.Experience using SystemVerilog and UVMProven software engineering skills including the understanding of object-oriented programming, data structures and algorithms.familiarity with the tools and processes for developing testbenches and finishing all aspects of the verification process.Good competency in developing verification flows, making the best use of EDA tools and good scripting skillsStrong communication skills and the ability to work well as part of a team.Dedicated with a focused approach to problem analysis and solving.Useful Skills:Team leadership and mentoring experienceMultiprocessing microarchitecture experience including knowledge of cache coherence and bus protocols e.g. AMBA5 CHI, AMBA4 ACE or AXIExperience in Formal Verification testbenches is a plus.