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| Job Location | London |
| Education | Not Mentioned |
| Salary | £40,000 - £65,000 per annum |
| Industry | Not Mentioned |
| Functional Area | Not Mentioned |
| Job Type | Permanent, full-time |
Hardware Verification Engineer - Greater LondonAvanti Recruitment have partnered with a high profile R&D group near London to recruit a Hardware Verification Engineer in to their heavyweight development team. You’ll play a key role in innovating the future of media processing hardware and architectures by applying your verification background to their market leading designs.For this role you’ll need a deep knowledge of UVM and implementing UVM testbenches, you’ll be someone that takes a proactive approach to verification - not just finding faults, but working closely with the design team on solutions too.You’ll be working with a team of 3 other Verification Engineers - all closely aligned with their HW development team and work on subsystem module verification, using state of the art IC test techniques for both module and top level verification in an environment where innovation is king and rewards are given as a direct result of your contributions and inputs.You’ll need:A good understanding / hands-on experience with IC verificationA demonstrable UVM background including setting up and configuring a UVM testbenchA firm grasp of System Verilog (bonus points for some VHDL too)You’ll be a problem solver, rather than just a problem finderAny exposure to ASIC or IC design in highly sought after (though this isn’t essential).In return you’ll get a great salary, an excellent benefits package, exposure to a state of the art hardware development environment where your work quite literally enables the technology of tomorrow, stacks of career development and progression available and first class training and mentoring from some of the most talented Engineers in the chip design industry globally.Click the apply button now for a call back or contact Dave at Avanti Recruitment for further information Required skills
Keyskills :
ASIC UVM Verification Verilog VHDL