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| Job Location | Cambridge |
| Education | Not Mentioned |
| Salary | £50,000 - £100,000 per annum |
| Industry | Not Mentioned |
| Functional Area | Not Mentioned |
| Job Type | Permanent, full-time |
JOB AD:In this position you will:Implement and validate ATPG structures, via:Partitioning for ATPG and hierarchical approachesATPG compression and serializationScan insertion and design rule fixingSTA constraints, Primetime execution and timing exception flowGate level simulation and debugValidate DFT structures, via:Synopsys SMS Memory BIST and repairIP BIST, typically for DDR and SERDES interfacesVHDL / Verilog design of test structuresSystem Verilog simulation of DFT test casesVector generation, translation and re-simulationUnderstand and improve test yields, address test vector instabilities, via:Validation of test structures across PVT (Vector bring-up and characterization)IP test enhancement and validation, especially high-speed digital interfacesAssist others in production test program development